1. Field of the Invention
This invention relates to a semiconductor memory device and a method of operation thereof, and more particularly to a dynamic type semiconductor memory device in which a sense amplifier is commonly used for a plurality of memory cell array blocks and an operating method thereof.
2. Description of the Background Art
FIG. 7 is a block diagram illustrating a configuration of a main section of a conventional dynamic random access memory (hereinafter referred to as DRAM) having 1M-bit memory capacity.
In a memory cell array 10 of FIG. 7, a plurality of word lines and bit lines are disposed to intersect one another, and memory cells are provided at their intersections. That is, a plurality of memory cells are arranged in a plurality of rows and columns. The memory cell array 10 is divided into four portions and each portion thereof is further divided into two memory cell array blocks 10a and 10b. The memory cell array 10 is thus divided into eight memory cell array blocks. Each of the memory cell array blocks 10a, 10b is of a 256.times.512 bit organization.
A row decoder 30 is disposed at the side portion of the memory cell array 10. Further, two column decoders 41 and 42 are disposed at the central section of the memory cell array 10. A decoder 30 selects any of the plurality of word lines in each memory cell array block 10a, 10b responsive to a row address signal. A plurality of memory cell array blocks 10a, 10b included in the memory cell array 10 are selected by a row address signal RA8. As shown in FIG. 7, if the row address signal RA8 is "1", four memory cell array blocks 10a (named A block) are selected and four memory cell array blocks 10b (named B block) are at a non-selected state. Conversely, if the row address signal RA8 is "0", four memory cell array blocks 10b are selected while four memory cell array blocks 10a are at the non-selected state.
A sense amplifier block 20 is disposed between the memory cell array blocks 10a and 10b in each portion of the memory cell array 10. This sense amplifier block 20 is of the configuration of a shared sense amplifier and is commonly used for two memory cell array blocks 10a and 10b. In each portion of the memory cell array 10, there is provided a switching signal generating circuit 60a generating a switching signal for connecting the sense amplifier block 20 to the memory cell array block 10a, and a switching signal generating circuit 60b generating a switching signal for connecting the sense amplifier block 20 to the memory cell array block 10b. For example, when the A block of the memory cell array 10 is selected as the row address signal RA8 is "1", the sense amplifier block 20 is connected to bit line pairs in the memory cell array block 10a responsive to a switching signal from the switching signal generating circuit 60a, while the sense amplifier block 20 is electrically separated from bit line pairs in the memory cell array block 10b responsive to a switching signal from the switching signal generating circuit 60b.
FIG. 8 is a circuit diagram illustrating the configuration of the main section of the DRAM in FIG. 7.
A plurality of bit line pairs and a plurality of word lines intersecting therewith are disposed in each of the memory cell array blocks 10a and 10b. In FIG. 8, a bit line pair BL, BL and a word line WL0 included in the memory cell array block 10a are typically illustrated, and a bit line pair BL, BL and a word line WL1 included in the memory cell array block 10b are also typically illustrated. A complementary signal appears on the bit lines BL and BL. Memory cells are provided at the intersections of the bit lines and word lines. A memory cell MC provided at the intersection of the bit line BL and word line WL0, and a memory cell MC provided at the intersection of the bit line BL and word line WL1 are typically illustrated in FIG. 8. Each memory cell MC is of an one-transistor one-capacitor configuration. That is, each memory cell MC is formed of a memory capacitor Cs for storing information and an N channel MOS transistor Q.sub.s.
An N channel-type sense amplifier 21 of flip-flop type and a P-channel type sense amplifier 22 of flip-flop type are provided between the memory cell array blocks 10a and 10b. These sense amplifiers 21 and 22 amplify a difference between the potentials of signals on the bit lines BL and BL. The N channel-type sense amplifier 21 is formed of N channel-type MOS transistors Q21 and Q22 while the P channel-type sense amplifier 22 is formed of P channel-type MOS transistors Q24 and Q25. These sense amplifiers 21 and 22 are activated by sense amplifier activating signals S0 and S0. An N channel type MOS transistor Q23 is turned on responsive to a sense amplifier activating signal S0 while a P channel-type MOS transistor Q26 is turned on responsive to a sense amplifier activating signal S0. Accordingly, the sense amplifier 21 discharges a bit line of low potential in the bit line pair BL, BL to a ground potential, while the sense amplifier 22 charges a bit line of high potential in the bit line pair BL, BL to a supply potential V.sub.CC. Each sense amplifier block 20 in FIG. 7 is formed of a plurality of N channel-type sense amplifiers and P channel-type sense amplifiers.
Since the memory cell array blocks 10a, 10b and the sense amplifier block 20 are of a shared sense amplifier configuration, there are provided a switching circuit 80a for electrically separating or connecting the bit line pair BL, BL in the memory cell array block 10a and the sense amplifiers 21 and 22, and a switching circuit 80b for electrically separating or connecting the bit line pair BL, BL in the memory cell array block 10b and the sense amplifiers 21 and 22. A switching circuit 80a is formed of N channel-type MOS transistors Q27, Q28 while the switching circuit 80b is formed of N channel-type MOS transistors Q29, Q30. The transistors Q27, Q28 have their gates supplied with a switching signal S1U from the switching signal generating circuit 60a shown in FIG. 7, while the transistors Q29, Q30 have their gates supplied with a switching signal S1L from the switching signal generating circuit 60b shown in FIG. 7. Both switching signals S1U and S1L are usually at the level of the supply potential V.sub.CC (hereinafter referred to as a V.sub.CC level).
Now, for example, when the potential of the word line WL0 goes to the "H" level so that information is read from the memory cell MC in the memory cell array block 10a, the switching signal S1L is at the level of ground potential (hereinafter referred to as a ground level) immediately before or at the same time the potential of the word line WL0 goes to the "H" level. Accordingly, the bit line pair BL, BL in the memory cell array block 10b is electrically separated from the sense amplifiers 21 and 22. The switching signal S1U subsequently goes to a higher level than the V.sub.CC level, so that the transistors Q27, Q28 become fully conductive, and the bit line pair BL, BL in the memory cell array block 10a is fully connected to the sense amplifiers 21 and 22.
When a column selecting signal Y supplied from column decoders 41 and 42 shown in FIG. 7 goes to the "H" level, N channel MOS transistors Q31 and Q32 are turned on, so that the information of sense nodes N1 and N2, which are common to both the sense amplifiers 21 and 22 is transmitted to an input and output line pair I/O, I/O.
Furthermore, an equalizing and precharging circuit 11 comprising N channel type MOS transistors Q33-Q35 is respectively connected to each bit line pair BL, BL of the memory cell array blocks 10a and 10b. In the standby periods before a memory cycle starts and after the memory cycle ends, the equalizing and precharging circuit 11 equalizes the potentials of respective bit lines of a corresponding bit line pair BL, BL responsive to an equalizing signal EQ, and precharges the bit line pair BL, BL to a prescribed precharging potential V.sub.BL. As above mentioned, since the switching signals S1U and S1L are at the V.sub.CC level in the standby period, the sense nodes N1 and N2 of the sense amplifiers 21 and 22 are also equalized and precharged.
Thus, the switching signals S1U and S1L are both usually at the V.sub.CC level; however, in memory operation, in order to connect the bit line pairs in the memory cell array blocks selected by the row address signals to the sense amplifiers, it is required that one of the switching signals S1U and S1L changes to a higher level than the V.sub.CC level while the other changes to the ground level.
FIG. 9 illustrates a circuit diagram of a switching signal generating circuit for generating a switching signal S1U or S1L. This switching signal generating circuit comprises N channel-type MOS transistors Q41-Q47 and capacitors C11, C12. In the case of the switching signal generating circuit 60a for generating the switching signal S1U, a transistor Q45 has its gate provided with a row address signal RA8. In the case of the switching signal generating circuit 60b for generating the switching signal S1L, the transistor Q45 has its gate provided with a row address signal RA8.
The operation of the switching signal generating circuit in FIG. 9 will now be described in reference to a timing chart of FIG. 10.
First of all, the operation of the switching signal circuit 60a for generating the switching signal S1U will be described. In a standby period, an input signal .phi..sub.P is at a higher level than the V.sub.CC level while an input signal .phi.3 is at the "L" level, and both the row address signals RA8 and RA8 are also at the "L" level. Accordingly, transistors Q41, Q42, Q43 shown in FIG. 9 are fully on while transistors Q45-Q47 are both off. The supply potential V.sub.CC is applied to the drains of the transistors Q41-Q43, so that the switching signal S1U outputted from an output terminal 61 is at the V.sub.CC level.
When the input signal .phi..sub.P then goes to the "L" level, the transistors Q41-Q43 are turned off. However, since the transistors Q45, Q47 are off, the switching signal S1U is maintained at the V.sub.CC level. When the row address signal RA8 then rises to the "H" level and then the row address signal RA8 is maintained at the "L" level, the transistors Q45, Q47 remain off since the row address signal RA8 is supplied to the gates of the transistors Q45, Q47. When the input signal .phi.3 rises to the "H" level thereafter, the gate potential of the transistor Q44 is boosted by the capacitor C11 so as to be a sufficiently higher level than V.sub.CC level. Further, the drain potential of the transistor Q44 is boosted by the capacitor C12 to be a sufficiently higher level than the V.sub.CC level. Accordingly, the switching signal S1U rises to a higher level than the V.sub.CC level via the transistor Q44. Finally, when the input signal .phi..sub.P rises to a higher level than the V.sub.CC level, the switching signal S1U goes back to the V.sub.CC level.
As described above, when the row address signal RA8 is at the "H" level, and the row address signal RA8 is at the "L" level, the switching signal S1U goes to a higher level than the V.sub.CC level.
The following description is about the case in which the row address signal RA8 falls down to the "L" level while the row address signal RA8 rises to the "H" level. The operation until the changes of the row address signals RA8 and RA8 is the same as the one mentioned above, so that a switching signal S1U is at the V.sub.CC level. As shown by a dashed line in FIG. 10, if the row address signal RA8 is maintained at the "L" level and the row address signal RA8 rises to the "H" level, the transistors Q45, Q47 are turned on. Accordingly, as shown by another dashed line in FIG. 10, the switching signal S1U goes to a ground level via the transistor Q45. The gate potential of the transistor Q44 also goes to a ground level via the transistors Q46, Q47. When the input signal .phi.3 rises to the "H" level, the drain potential of the transistor Q44 is boosted to a sufficiently higher level than the V.sub.CC level by the capacitor C12. However, since the gate potential of the transistor Q44 is at the ground level via the transistors Q46, Q47, and an output terminal 61 is grounded via the transistor Q45, the switching signal S1U remains at the ground level.
Both the row address signals RA8 and RA8 then fall down to the "L" level. The input signal .phi..sub.P remains at the "L" level at this time, so that the transistors Q41-Q43 are kept off while the switching signal S1U is maintained at the ground level. Finally, when the input signal .phi..sub.P rises to a sufficiently higher level than the V.sub.CC level, the switching signal S1U changes to the V.sub.CC level.
Thus, if the row address signal RA8 is at the "" level and the row address signal RA8 is at the "H" level, the switching signal S1U goes to the ground level.
In the case of the switching signal generating circuit 60b for generating the switching signal S1L, the transistor Q45 has its gate provided with the row address signal RA8 substituted for the row address signal RA8.
The operation of the switching signal generating circuits 60a and 60b is summarized in FIG. 11. That is, when all the row address signals RA8 and RA8 are at the "L" level, both the switching signals S1U and S1L are at the V.sub.CC level. Further, when the row address signal RA8 rises to the "H" level and the row address signal RA8 falls down to the "L" level, the switching signal S1U rises to a higher level than the V.sub.CC level and the switching signal S1L goes down to the "L" level (ground level). On the contrary, when the row address signal RA8 goes down to the "L" level and the row address signal RA8 goes to the "H" level, the switching signal S1U falls down to the "L" level while the switching signal S1L rises to a higher level than the V.sub.CC level.
As aforementioned, in a conventional DRAM shown in FIG. 7, the switching signal generating circuit 60a having the circuit configuration of FIG. 9 is provided at each memory cell array block 10a, and the switching signal generating circuit 60 b having the circuit configuration of FIG. 9 is provided at each memory cell array block 10b. The capacitor C12 for boosting the switching signal S1U or S1L to a higher level than the V.sub.CC level, requires a larger area than the other elements. In the above described conventional DRAM, while boosting operations are performed in the four switching signal generating circuits 60a, they are not performed in the other four switching signal generating circuits 60b. On the contrary, while the boosting operations are performed in the four switching signal generating circuits 60b, they are not performed in the other four switching signal generating circuits 60a. Nevertheless, one switching signal generating circuit 60a and one switching signal generating circuit 60b are required for each memory cell array block 10a and 10b, respectively. Therefore, a large number of capacitors necessary for boosting operations need to be formed, so that there is a problem that a large circuit area is needed.
It can also be conceived that one switching signal generating circuit is provided for four memory cell array blocks 10a, and one switching signal generating circuit is provided for four memory cell array blocks 10b. However, in this case, the total area of capacitors included in one switching signal generating circuit is larger than the total area of capacitors included in four switching signal generating circuits having the circuit configuration of FIG. 7.